/**
  ******************************************************************************
  * @file    Libraries/Device/TS32Fx/TS32Fx_LL_Driver/inc/ts32fx_ll_sysctrl.h
  * @author  TOPSYS Application Team
  * @version V1.0.0
  * @date    02-11-2018
  * @brief   This file contains all the SYSCTRL LL firmware functions.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2018 TOPSYS</center></h2>
  *
  *
  *
  ******************************************************************************
  */ 
  
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TS32FX_LL_SYSCTRL_H
#define __TS32FX_LL_SYSCTRL_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "ts32fx.h"
     
/** @addtogroup TS32Fx_StdPeriph_Driver TS32Fx Driver
  * @{
  */
     
/** @addtogroup sysctrl_interface_gr SYSCTRL Driver
  * @ingroup  TS32Fx_StdPeriph_Driver
  * @{
  */ 

/** @addtogroup SYSCTRL_LL_Driver SYSCTRL LL Driver
  * @ingroup  sysctrl_interface_gr
  * @brief Mainly the driver part of the SYSCTRL module, which includes \b SYSCTRL \b Register 
  * \b Constants, \b SYSCTRL \b Exported \b Constants, \b SYSCTRL \b Exported \b Struct, \b SYSCTRL
  * \b Data \b transfers \b functions, \b SYSCTRL \b Initialization \b and \b SYSCTRL \b Configuration 
  * \b And \b Interrupt \b Handle \b function.
  * @{
  */

/* Exported types ------------------------------------------------------------*/

/* Exported constants --------------------------------------------------------*/

/** @defgroup SYSCTRL_LL_Register_Constants SYSCTRL LL Register Constants
  * @ingroup  SYSCTRL_LL_Driver
  * @brief    SYSCTRL LL register constant table definition
  *
  *
@verbatim   
  ===============================================================================
                                Register Constants
  ===============================================================================  
  
    Register Constants mainly encapsulates each bit in each group in the SYSCTRL 
    register. In the process of configuration, the macro definition can be directly 
    called to configure the SYSCTRL register, mainly for convenience. Understand the 
    configuration of the SYSCTRL.
    
@endverbatim
  *
  * @{
  */

/***** SYSTEM Register ********/

/* configure SYS_CON0 regiter */
/*! reset GPIOA/GPIOB/GPIOC configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_GPIO_FINISH_RESET       (1UL << 15)
/*! reset KeyADC configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_KEYADC_FINISH_RESET     (1UL << 13)
/*! reset TouchKey&Led driver configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_TKEY_LED_FINISH_RESET   (1UL << 12)
/*!  reset GPIO debounce relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_DBS_FINISH_RESET        (1UL << 10)
/*! reset CRC relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_CRC_FINISH_RESET        (1UL << 9)
/*! reset WDT relative configure register  
 *0: reset  
 *1: finish reset  
*/
#define LL_SYSCTRL_CON0_WDT_FINISH_RESET        (1UL << 8)
/*! reset UART1 relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_UART1_SINISH_RESET      (1UL << 5)
/*! reset UART0 relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_UART0_SINISH_RESET      (1UL << 4)
/*! reset SPI0 relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_SPI0_FINISH_RESET       (1UL << 3)
/*! reset SPI1 relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_SPI1_FINISH_RESET       (1UL << 2)
/*! reset TIMERs relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_TIMER_FINISH_RESET      (1UL << 1)
/*! reset WDT system domain relative configure register  
 * 0: reset  
 * 1: finish reset  
 */
#define LL_SYSCTRL_CON0_WDT_SYS_FINISH_RESET    (1UL << 0)


/******** configure SYS_CON1 regiter **********/
/*! NMI Pin polarity inverse choose  
 * 0: high level pin trigger NMI  
 * 1: low level pin trigger NMI  
 */
#define LL_SYSCTRL_CON1_NMI_INV_SEL             (1UL << 10)
/*! enable or disable SWD model  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_SWD_EN                  (1UL << 8)
/*! VCC low voltage detecter quickly reset GPIO status register  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_LVDVCC_RST_EN           (1UL << 7)
/*! Enable internal clock source output to PB7  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_CLK_TEST_OUT_EN         (1UL << 6)
/*! Enable system bus access out of side memory zone return error response  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_SYS_ERRRESP_EN          (1UL << 5)
/*! Enable system bus access out of side memory zone trigger NMI interrupt  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_SYS_ERRINT_EN           (1UL << 4)
/*! Monitor XOSC loss trigger NMI interrupt  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_HOSC_LOSSNMI_EN         (1UL << 3)
/*! Enable PA11 as receiver event to CPU  
 * 0: diasble  
 * 1: enable  
 */
#define LL_SYSCTRL_CON1_RXEV_EN                 (1UL << 2)
/*! Enable PA10 as external NMI input to CPU  
 * 0: diasble  
 * 1: enable  
*/
#define LL_SYSCTRL_CON1_NMI_INT_EN              (1UL << 1)
/*! Enable system lockup trigger system reset  
 */
#define LL_SYSCTRL_CON1_LOCKUP_EN               (1UL << 0)


/********** configure SYS_CON2 regiter *********/
/*! PortC debounce enable register [3:0] for PC3-PC0  
 * n pc3~pc0 bit map  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CON2_PC3_0_DEB_EN(n)         (((n) & 0xF) << 28)
/*! PortB debounce enable register [15:0] for PB15-PB0  
 * n pb15~pb0 bit map  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CON2_PB15_0_DEB_EN(n)        (((n) & 0xFFFF) << 12)
/*! PortA debounce enable register [11:0] for PA11-PA0  
 * n pa11~pa0 bit map  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CON2_PA11_0_DEB_EN(n)        (((n) & 0xFFF) << 0)

/*************** configure SYS_CON3 regiter *****************/
/*! Enable PC9 remap  
 * 0: disable  
 * 1: enable. PC9 remap to PC7  
 */
#define LL_SYSCTRL_CON3_PC9_REMAP_EN            (1UL << 17)
/*! Enable PC8 remap  
 * 0: disable  
 * 1: enable. PC8 remap to PC7  
 */
#define LL_SYSCTRL_CON3_PC8_REMAP_EN            (1UL << 16)
/*! Enable PC5 remap  
 * 0: disable  
 * 1: enable. PC5 remap to PC6  
 */
#define LL_SYSCTRL_CON3_PC5_REMAP_EN            (1UL << 15)
/*! Enable PC4 remap  
 * 0: disable  
 * 1: enable. PC4 remap to PC6  
 */
#define LL_SYSCTRL_CON3_PC4_REMAP_EN            (1UL << 14)
/*! Enable PB14/PB15 remap  
 * 0: disable  
 * 1: enable. PB14/PB15 remap to PB7  
 */
#define LL_SYSCTRL_CON3_PB14_15_REMAP_EN        (1UL  <<  13)
/*! Enable PB12/PB13 remap  
 * 0: disable  
 * 1: enable. PB12/PB13 remap to PB6  
 */
#define LL_SYSCTRL_CON3_PB12_13_REMAP_EN        (1UL << 12)
/*! Enable PB10/PB11 remap  
 * 0: disable  
 * 1: enable. PB10/PB11 remap to PB5  
 */
#define LL_SYSCTRL_CON3_PB10_11_REMAP_EN        (1UL << 11)
/*! Enable PB8/PB9 remap  
 * 0: disable  
 * 1: enable. PB8/PB9 remap to PB4  
 */
#define LL_SYSCTRL_CON3_PB8_9_REMAP_EN          (1UL << 10)
/*! Enable PB6/PB7 remap  
 * 0: disable  
 * 1: enable. PB6/PB7 remap to PB3  
 */
#define LL_SYSCTRL_CON3_PB6_7_REMAP_EN          (1UL << 9)
/*! Enable PB4/PB5 remap  
 * 0: disable  
 * 1: enable. PB4/PB5 remap to PB2  
 */
#define LL_SYSCTRL_CON3_PB4_5_REMAP_EN          (1UL << 8)
/*! Enable PB2/PB3 remap  
 * 0: disable  
 * 1: enable. PB2/PB3 remap to PB1  
 */
#define LL_SYSCTRL_CON3_PB2_3_REMAP_EN          (1UL << 7)
/*! Enable PB1 remap  
 * 0: disable  
 * 1: enable. PB1 remap to PB0  
 */
#define LL_SYSCTRL_CON3_PB0_1_REMAP_EN          (1UL  << 6)

/*! PortC debounce enable register [9:4] for PC9-PC4  
 * n pc9~pc4 bit map  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CON3_PC9_4_DEB_EN(n)         (((n) & 0x3F) << 0)


/************configure CLK_CON0 regiter*****************/

/*! Make CLK OUTPUT select HIRC 26M or RingClk  
 * 0: select HIRC 26M  
 * 1: select RingClk  
 */
#define LL_SYSCTRL_CLK_CON0_RINGOUT_SEL         (1UL << 16)
/*! compartor work clock select  
 * 00: sys_clk  
 * 01: divider output from HIRC 26M  
 * 10: LIRC 32K  
 * 11: XOSC  
 */
#define LL_SYSCTRL_CLK_CON0_COMP_CLK_SEL(n)     (((n) &0x3) << 14)
/*! pll output clock select  
 * 00 :select phase 4 output  
 * 01 :select phase 5 output  
 * 10 :select phase 6 output  
 * 11 :select phase 7 output  
 */
#define LL_SYSCTRL_CLK_CON0_PULL_SEL(n)         (((n) &0x3) << 12)
/*! GPIOC debouce work clock select  
 * 00: XOSC  
 * 01: divider output from HIRC 26M  
 * 10: sys_clk  
 * 11: LIRC 32K  
 */
#define LL_SYSCTRL_CLK_CON0_GPIOC_DBS_SEL(n)    (((n) &0x3) << 10)
/*! GPIOB debouce work clock select  
 * 00: sys_clk  
 * 01: divider output from HIRC 26M  
 * 10: LIRC 32K  
 * 11: XOSC  
 */
#define LL_SYSCTRL_CLK_CON0_GPIOB_DBS_SEL(n)    (((n) &0x3) << 8)
/*! GPIOA debouce work clock select  
 * 00: sys_clk  
 * 01: divider output from HIRC 26M  
 * 10: LIRC 32K  
 * 11: XOSC  
 */
#define LL_SYSCTRL_CLK_CON0_GPIOA_DBS_SEL(n)    (((n) &0x3) << 6)
/*! Pll reference clock select  
 * 00: HIRC 26M  
 * 01: LIRC 32K  
 * 10: HIRC 26M  
 * 11: XOSC  
 */
#define LL_SYSCTRL_CLK_CON0_PLL_REFCLK_SEL(n)  (((n) &0x3) << 4)
/*! Output clock select  
 * 00: pll_clk  
 * 01: HIRC 26M or RingClk  
 * 10: LIRC 32K  
 * 11: XOSC  
 */
#define LL_SYSCTRL_CLK_CON0_CLOCK_TO_IO_SEL(n)  (((n) &0x3) << 2)

/*! system clock select  
 * 00: LIRC 32K  
 * 01: XOSC  
 * 10: HIRC 26M  
 * 11: pll_clk  
 */
#define LL_SYSCTRL_CLK_CON0_SYS_CLK_SEL(n)      (((n) &0x3) << 0)


/**************** configure CLK_CON1 regiter *****************/
/*! Clock to IO divider  
 * 00: divide by 1  
 * 01: divide by 2  
 * 10: divide by 3  
 * 11: close clock output  
 */
#define LL_SYSCTRL_CLK_TO_IO_DIV(n)             ((n & 0x03) << 28)
/*! HIRC 26M clock divider  
 * 0x0: divide by 1  
 * 0x1: divide by 2  
 * ...  
 * 0xe divide by 15  
 * 0xf close HIRC divide clock  
 */
#define LL_SYSCTRL_CLK_CON1_HIRC_CLK_DIV(n)     (((n) & 0xF) << 24)
/*!APB1 clock divider  
 * 0x00: divide by 1  
 * 0x01: divide by 2  
 * ...  
 * 0xfe: divide by 255  
 * 0xff: close tk hclk  
 */
#define LL_SYSCTRL_CLK_CON1_TK_DIV(n)           (((n) & 0xFF) << 16)
/*!APB1 clock divider  
 * 0x0: divide by 1  
 * 0x1: divide by 2  
 * ...  
 * 0xe: divide by 15  
 * 0xf: close apb1_clk  
 */
#define LL_SYSCTRL_CLK_CON1_APB1_CLK_DIV(n)     (((n) & 0xF) << 12)
/*!APB0 clock divider  
 * 0x0: divide by 1  
 * 0x1: divide by 2  
 * ...  
 * 0xe: divide by 15  
 * 0xf: close apb0_clk  
 */
#define LL_SYSCTRL_CLK_CON1_APB0_CLK_DIV(n)     (((n) & 0xF) << 8)
/*!System clock divider  
 * 0x00: divide by 1  
 * 0x01: divide by 2  
 * ...  
 * 0xfe: divide by 255  
 * 0xff: close sys_clk  
 */
#define LL_SYSCTRL_CLK_CON1_SYS_CLK_DIV(n)      (((n) & 0xFF) << 0)

/****************configure CLK_CON2 regiter*************/
/*! Enable HXOSC test output  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_HXOSC_TSOUT_EN      (1UL << 30)
/*! CP mode enable cpu clock  
 * 0: disable  
 * 1: enable  
*/
#define LL_SYSCTRL_CLK_CON2_CP_CLK_EN           (1UL << 29)
/*! Enable ATE clock input  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TEST_CLK_EN         (1UL << 28)
/*! Enable comparator clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_COMP_CLK_EN         (1UL << 27)
/*! Enable CRC clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_CRC_CLK_EN          (1UL << 25)
/*! Enable eflash erase/program clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_EFLASH_MEM_CLK_EN   (1UL << 24)
/*! Enable uart1 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_UART1_CLK_EN        (1UL << 18)
/*! Enable uart0 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_UART0_CLK_EN        (1UL << 17)
/*! Enable spi1 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_SPI1_CLK_EN         (1UL << 16)
/*! Enable spi0 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_SPI0_CLK_EN         (1UL << 15)
/*! Enable timer5 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TIMER5_CLK_EN       (1UL << 13)
/*! Enable timer3 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TIMER3_CLK_EN       (1UL << 12)
/*! Enable timer2 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TIMER2_CLK_EN       (1UL << 11)
/*! Enable timer1 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TIMER1_CLK_EN       (1UL << 10)
/*! Enable timer0 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TIMER0_CLK_EN       (1UL << 9)
/*! Enable watchdog clock
 * 0: disable
 * 1: enable
 */    
#define LL_SYSCTRL_CLK_CON2_WDT_CLK_EN          (1UL << 8)
/*! Enable watchdog system clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_WDT_SYS_CLK_EN      (1UL << 7)
/*! Enable timer4 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TIMER4_CLK_EN       (1UL << 6)
/*! Enable LED driver clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_LED_CLK_EN          (1UL << 4)
/*! Enable touchkey clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_TK_CLK_EN           (1UL << 3)
/*! Enable SRAM clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_SRAM0_CLK_EN        (1UL << 2)
/*! Enable ahb1 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_AHB1_CLK_EN         (1UL << 1)
/*! Enable ahb0 clock  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON2_AHB0_CLK_EN         (1UL << 0)  


/********************configure LL_SYSCTRL_CLK_CON3 regiter****************/
/*! RingClk enable  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON3_RING_EN                (1UL << 27)
/*! RingClk divide 2 enable  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON3_RING_DIV2_EN           (1UL << 26)
/*! XOSC internal LDO enable
 * 0: disable
 * 1: enable
 */
#define LL_SYSCTRL_CLK_CON3_HXOSC_LDO_EN           (1UL << 25)
/*! VDD test enable; output to VTSOUT  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON3_HRCOSC_VTEST2_EN       (1UL << 24)
/*! VDDOSC test enable; output to VTSOUT  
 * 0: disable  
 * 1: enable  
*/
#define LL_SYSCTRL_CLK_CON3_HRCOSC_VTEST1_EN       (1UL << 23)
/*! LDO reference select  
 * 0: Voltage bias;  
 * 1: Current  
 */
#define LL_SYSCTRL_CLK_CON3_HRCOSC_VSEL            (1UL << 22)
/*! Freq control  
 * 0x00: lowest  
 * ....  
 * 0x7f: highest;  
 */
#define LL_SYSCTRL_CLK_CON3_HRCOSC_SC(n)           (((n) & 0x7F) << 15)
/*!RCOSC LDO Voltage selection  
 * 0: 1.5v;  
 * 1: 1.6v  
 */
#define LL_SYSCTRL_CLK_CON3_HRCOSC_LDOS            (1UL << 14)
/*! RCOSC enable signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON3_HRCOSC_EN              (1UL << 13)
/*! HIRC 26M ready status bit(ro)  
 * 0: not ready  
 * 1: ready  
 */
#define LL_SYSCTRL_CLK_CON3_HIRC_26M_READY_STATE   (1UL << 12)
/*! Setting XOSCI(SC[3:2])/XOSCO(SC[1:0])  
 * reset: 0x1a  
 */
#define LL_SYSCTRL_CLK_CON3_HXOSC_SC               (((n) & 0x1F) << 7)
/*! XOSC Dual PIN feedback resistor control;  
 * reset: 1  
 */
#define LL_SYSCTRL_CLK_CON3_HXOSC_RES              (((n) & 0x3) << 5)
/*! XOSC enable signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_CLK_CON3_HXOSC_EN               (1UL << 3)
/*! Driver ability control  
 * 000: XTAL=12M  
 * 011: XTAL=24M/26M  
 */
#define LL_SYSCTRL_CLK_CON3_HXOSC_DRV_ABILITY(n)   (((n) & 0x7) << 0)


/******************* configure HOSC_MNT regiter *********************/
/*! xosc normal work count high limit  
 * reset: 0x1450  
 */
#define LL_SYSCTRL_HOSC_MNT_XOSC_HIGH_LIMIT(n)     (((n) & 0xFFFF) << 16) 
/*! enable xosc work monitor  
 * 0: disable  
 * 1: enable  
 */    
#define LL_SYSCTRL_HOSC_MNT_HOSC_MNT_EN            (1UL << 15)
/*! Read : the pending which indicate the failure of external xosc  
 * Write:  
 * 0:clear pending  
 * 1:nothing happens  
 */
#define LL_SYSCTRL_HOSC_MNT_HOSC_LOSS_PEND_CLR     (1UL << 14)
/*! enable hardware auto switch osc clock from xosc to  
 * HIRC when detect the failure of external osc  
 * 0:not automatic switch  
 * 1:automatic switch  
 */
#define LL_SYSCTRL_HOSC_MNT_HOSC_LOSS_SW_EN        (1UL << 13)
/*! xosc normal work count low limit  
 * reset: 0xa7  
 */
#define LL_SYSCTRL_HOSC_MNT_XOSC_LOW_LIMIT(n)      (((n) & 0x1FFF) << 0)


/**************** configure SYS_ERR0 regiter ****************/
/*
                                             clk_err condition  
                                        lirc disable           hirc          disable            xosc disable | xosc ldo disable  
* sys_clk_sel_lirc                              v  
* sys_clk_sel_hirc                                               v  
* sys_clk_sel_xosc                                                              v  
* sys_clk_sel_pll & pll_ref_sel_lirc            v  
* sys_clk_sel_pll & pll_ref_sel_hirc                             v  
* sys_clk_sel_pll & pll_ref_sel_xosc                                            v  
*/
/*! clock use error status.  
 *1: clock use error happen,this bit can be set by hardware.clear by software  
 *0: clock use error not happen  
 */        
#define LL_SYSCTRL_SYSERR0_CLK_ERR_PEND             (1UL << 1)
/*! Indicate the error pending of bus operation out of side memories.  
 *if set sys_err_int_en, this pending will make NMI interrupt happens  
 */
#define LL_SYSCTRL_SYSERR0_SYS_ERR_PEND             (1UL << 0)


/**************** configure WKUP_CON0 regiter ****************/
/*! Indicate the relative IO edge detected(ro)  
 *0: not detected  
 *1: detected  
*/
#define LL_SYSCTRL_WKUP_CON0_WAKEUP_PEND_GET(p_sysctrl)           (((p_sysctrl->WKUP_CON0) >> 24) & 0xF)
/*! Write 1 to clear the relative pending
 */
#define LL_SYSCTRL_WKUP_CON0_WAKEUP_PEND(n)                       (((n) & 0xF) << 16)
/*! Choose which edge to monitor of chosen external port  
 * 0: the rising edge  
 * 1: the falling edge  
 */
#define LL_SYSCTRL_WKUP_CON0_WKUP_EDGE_CHOOSE(n)                  (((n) & 0xF) << 8)
/*! Enable monitor the edges change of chosen external port  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_HWKUP_CON0_WKUP_EN(n)                          (((n) & 0xF) << 0)

/************************ configure LP_CON0 regiter *****************/
/*! Automatic enable HIRC 26M when xosc monitor loss event happen  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_LP_CON0_HIRC_AUTO_EN                            (1UL << 6)
/*! Enable LIRC  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_LP_CON0_RC32K_SOFT_EN                           (1UL << 5)
/*! Enable automatic shut down LIRC when enter sleep mode  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_LP_CON0_RC32K_AUTO_DIS                          (1UL << 4)
/*! Enable automatic shut down HIRC 26M,when stopclk or sleep mode  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_LP_CON0_HIRC_AUTO_DIS                           (1UL << 3)

/*! Enable automatic shut down sram CE when enter stopclk or sleep mode  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_LP_CON0_SRAM0_AUTO_ENABLE                       (1UL << 2)

/*! stopclk mode  
 * 0:not enter stopclk mode  
 * 1:enter stopclk mode  
 */
#define LL_SYSCTRL_LP_CON0_STOP_CLK                                (1UL << 1)
/*! sleep mode  
 * 0:not enter sleep mode  
 * 1:enter sleep mode  
 */
#define LL_SYSCTRL_LP_CON0_SLEEP                                   (1UL << 0)

/****************** configure MBIST_CON0 regiter ************/
/*! mbist fail pending  
 * Read:  
 * Indicate MBIST fail pending  
 * Write:  
 * Write 1 to clear this fail pending  
*/
#define LL_SYSCTRL_MBIST_CON0_MBIST_FAIL_PEND_CLR                  (1UL << 20)
/*! mbist test done pending  
 * Read:  
 * Indicate MBIST done pending  
 * Write:  
 * Write 1 to clear this done pending  
 */
#define LL_SYSCTRL_MBIST_CON0_MBIST_TST_PEND_CLR                   (1UL << 19)
/*! Mbist clock enable  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_MBIST_CON0_MBIST_CLK_EN                         (1UL << 18)
/*! Enable rf1p memory mbist debug  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_MBIST_CON0_MBIST_RF1P_DEBUG_EN                  (1UL << 11)
/*! rf1p mbist test run  
 * 0: hold  
 * 1: run  
 */ 
#define LL_SYSCTRL_MBIST_CON0_MBIST_RF1P_RUN                       (1UL << 10)
/*! Enable rf1p mbist test  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_MBIST_CON0_MBIST_RF1P_TEST_EN                   (1UL << 9)

/************* configure CHIP_IDCN regiter ********************/
/*! Design change note version(ro)  
 * default: 0  
*/
#define LL_SYSCTRL_CHIP_IDCN_DCN_GET(p_sysctrl)                    (((p_sysctrl->CHIP_IDCN) >> 16) & 0xFF)
/*! Design change note version(ro)  
 * default: 0x1001  
*/
#define LL_SYSCTRL_CHIP_IDCN_ID_GET(p_sysctrl)                     (((p_sysctrl->CHIP_IDCN) >> 0) & 0xFFFF)


/************* configure MODE_REG regiter ********************/
/*! CP mode pending(ro)  
 * 0: chip is not cp mode  
 * 1: chip is cp mode  
*/
#define LL_SYSCTRL_MODE_CP_MODE(p_sysctrl)                         (((p_sysctrl->MODE_REG) >> 1) & 0x1)


/************* configure PMU_CON0 regiter ********************/
/*! LED lower current drive signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_LED_LDRV_EN                            (1UL << 14)
/*! LED bias enable signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_LED_BIAS_EN                            (1UL << 13)
/*! Temperature Sensor enable signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_TSEN_EN                                (1UL << 12)
/*! PMU VI2 Enable signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_PMU_V2IEN_EN                           (1UL << 11)
/*! BG in Low Power Mode signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_PMU_BGLOWP_EN                          (1UL << 10)
/*! VBG Buffer enable signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_PMU_BGBUF_EN                           (1UL << 9)
/*!VDD voltage select signal  
 * 0000=1.50@default  
 * 0001=1.10  
 * 0010=1.15  
 * 0011=1.20  
 * 0100=1.25  
 * 0101=1.30  
 * 0110=1.35  
 * 0111=1.40  
 * 1000=1.45  
 * 1001=1.05  
 * 1010=1.55  
 * 1011=1.60  
 * 1100=1.65  
 * 1101=1.70  
 * 1110=1.75  
 * 1111=1.80  
 */
#define LL_SYSCTRL_PMU_CON0_LDO_SET(n)                             (((n)&0xF) << 5)
/*! VDD LDO Pull down 5mA select signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_LDO_PD5MA_EN                           (1UL << 4)
/*! Enable VDD LDO Pull down 2.5mAselect signal  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_LDO_PD2P5MA_EN                         (1UL << 3)
/*! Enable low power work mode of PMU  
 * 0: disable  
 * 1: enable  
 */
#define LL_SYSCTRL_PMU_CON0_LPLDO_EN                               (1UL << 2)
/*! VBG trimming control  
 * 00=1.206(default)  
 * 01=1.181  
 * 10=1.232  
 * 11=1.257  
 * step=25mv  
 */
#define LL_SYSCTRL_PMU_CON0_BGTRIM_SET(n)                          (((n)&0x3) << 0)


/****************** configure RPCON regiter ******************/
/*! Write 1 to clear lockup reset pending
 */
#define LL_SYSCTRL_RPCON_UART0_UPDATE_RESET_PEND_CLR               (1UL << 19)
/*! Write 1 to clear lockup reset pending
 */
#define LL_SYSCTRL_RPCON_LOCKUP_RESET_PEND_CLR                     (1UL << 18)
/*! Write 1 to clear soft reset pending
 */
#define LL_SYSCTRL_RPCON_SORT_RESET_PEND_CLR                       (1UL << 17)
/*! Write 1 to clear sleep_pending
 */
#define LL_SYSCTRL_RPCON_SLEEP_STA_PEND_CLR                        (1UL << 16)
/*! Uart0 update event happend. pending(ro)
 */
#define LL_SYSCTRL_RPCON_UART0_UPDATE_PEND_GET(p_sysctrl)          (((p_sysctrl->RPCON) >> 3) & 0x1)
/*! When happen lockup reset, this bit will record this reset pending until cpu to clear it(ro).  
 * 0: not happen lockup reset  
 * 1: lockup reset have happend  
 */
#define LL_SYSCTRL_RPCON_LOCK_RESET_PEND_GET(p_sysctrl)             (((p_sysctrl->RPCON) >> 2) & 0x1)
/*! Write 1 to this bit will make chip to reset. which reset can make Eflash re-fetch NVR & main data. 
 * 0: not enable soft reset  
 * 1: enable soft reset and recording this reset pending here  
 */
#define LL_SYSCTRL_RPCON_SOFT_RESET_PEND                            (1UL << 1)
/*! Write LP_CON[0] will record sleep mode pending even after port wakeup system reset.  
 */
#define LL_SYSCTRL_RPCON_SLEEP_PEND_GET(p_sysctrl)                  (((p_sysctrl->RPCON) >> 0) & 0x1)



/**
  * @}
  */

/** @defgroup SYSCTRL_LL_Exported_Constants SYSCTRL LL Exported Constants
  * @ingroup  SYSCTRL_LL_Driver
  * @brief    SYSCTRL LL external constant definition
  *
@verbatim   
  ===============================================================================
                                Exported Constants
  ===============================================================================  
  
    Exported Constants mainly restricts the partial configuration of the abstraction 
    layer by using the form of enumeration to facilitate the use and understanding of 
    the module configuration. For the specific enumeration meaning, please refer to 
    the annotation of each module.

@endverbatim
  *
  * @{
  */
  
/***** DRIVER API *****/



/***** LL API *****/

/* set SYS_KEY regiter */
/*! Write 0x3fac87e4 to enable all system register write enable,Set sys_keyother value will  
 * clear this bitother value will clear this bit.Read return sys_key status  
 * 0:lock all system register wirte  
 * 1:unlock all system register write  
 */
#define LL_SYSCTRL_KEY_UNLOCK(p_sysctrl)                 (p_sysctrl->SYS_KEY = 0x3fac87e4)                      
#define LL_SYSCTRL_KEY_LOCK(p_sysctrl)                   (p_sysctrl->SYS_KEY = 0)
  
/***** LL API AND DRIVER API *****/



/**
  * @}
  */

/** @defgroup SYSCTRL_LL_Exported_Struct SYSCTRL LL Exported Struct
  * @ingroup  SYSCTRL_LL_Driver
  * @brief    SYSCTRL LL external configuration structure definition
  *
@verbatim   
  ===============================================================================
                                Exported Struct
  ===============================================================================  

    Exported Struct mainly extracts the SYSCTRL registers from the API, and abstracts 
    the structure. As long as it implements the low coupling between the registers 
    and the registers, the user only needs to configure the structure of the abstraction 
    layer and call hal_sysctrl_init. Function, you can configure the SYSCTRL module without 
    involving the configuration of the collective register.

@endverbatim
  *
  * @{
  */


/**
  * @}
  */

/** @defgroup SYSCTRL_LL_Interrupt SYSCTRL LL Interrupt Handle function
  * @brief   SYSCTRL LL Interrupt Handle function
  *
@verbatim   
  ===============================================================================
                        Interrupt Handle function
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the SYSCTRL  
    Interrupt Handle function.

    how to use?

    The SYSCTRL interrupt handler uses a callback method that reserves the interface 
    to the user in the form of a callback function. The client needs to initialize 
    the callback function when initializing the SYSCTRL in order for the interrupt to 
    be processed normally. 
   
@endverbatim
  *
  * @{
  */



/**
  * @}
  */
  
/** @defgroup SYSCTRL_LL_Inti_Cfg SYSCTRL LL Initialization And Configuration
  * @brief    SYSCTRL LL Initialization And Configuration
  *
@verbatim   
  ===============================================================================
                        Initialization And Configuration
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the SYSCTRL data 
    Initialization and Configuration.
    
    how to use?

@endverbatim
  *
  * @{
  */



/**
  * @}
  */
  
/** @defgroup SYSCTRL_LL_Data_Transfers SYSCTRL LL Data transfers functions
  * @brief    SYSCTRL LL Data transfers functions 
  *
@verbatim   
  ===============================================================================
                            Data transfers functions
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the SYSCTRL data 
    transfers and receive.
  
@endverbatim
  *
  * @{
  */

/**
  * @brief swd disable 
  * @param None  
  * @note  if need using SWD pin as gpio, you need call this function to disable swd
  * @retval None  
  */
void swd_disable(void);


/**
  * @}
  */

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

/**
  * @}
  */

/**
  * @}
  */

#endif //__TS32FX_LL_SYSCTRL_H

/*************************** (C) COPYRIGHT 2018 TOPSYS ***** END OF FILE *****/
